vishay siliconix SI1902DL document number: 71080 s11-2043-rev. j, 17-oct-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 dual n-channel 20 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfets: 2.5 v rated ? 100 % r g tested ? compliant to rohs directive 2002/95/ec notes: a. surface mounted on 1" x 1" fr4 board. product summary v ds (v) r ds(on) ( ? )i d (a) 20 0.385 at v gs = 4.5 v 0.70 0.630 at v gs = 2.5 v 0.54 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol 5 s steady state unit drain-source voltage v ds 20 v gate-source voltage v gs 12 continuous drain current (t j = 150 c) a t a = 25 c i d 0.70 0.66 a t a = 85 c 0.50 0.48 pulsed drain current i dm 1 continuous source current (diode conduction) a i s 0.25 0.23 maximum power dissipation a t a = 25 c p d 0.30 0.27 w t a = 85 c 0.16 0.14 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t ?? 5 s r thja 360 415 c/w steady state 400 460 maximum junction-to-foot (drain) steady state r thjf 300 350 m arkin g c ode pa x x lot t yy y sot-363 sc-70 (6-leads) 6 4 1 2 3 5 to p v iew s 1 g 1 d 2 d 1 g 2 s 2 yy part # code marking code pa lot traceability and date code ordering information: SI1902DL-t1-e3 (lead (pb)-free with tape and reel) SI1902DL-t1-ge3 (lead (pb)-free and halogen-free)
www.vishay.com 2 document number: 71080 s11-2043-rev. j, 17-oct-11 vishay siliconix SI1902DL this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics (25 c, unless otherwise noted) specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.6 1.5 v gate-body leakage i gss v ds = 0 v, v gs = 12 v 100 na zero gate voltage drain current i dss v ds = 16 v, v gs = 0 v 1 a v ds = 16 v gs = 0 v, t j = 85c 5 on-state drain current a i d(on) v ds ? 5 v, v gs = 4.5 v 1 a drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 0.66 a 0.320 0.385 ? v gs = 2.5 v, i d = 0.40 a 0.560 0.630 forward transconductance a g fs v ds = 10 v, i d = 0.66 a 1.5 s diode forward voltage a v sd i s = 0.23 a, v gs = 0 v 0.8 1.2 v dynamic b total gate charge q g v ds = 10 v, v gs = 4.5 v, i d = 0.66 a 0.8 1.2 nc gate-source charge q gs 0.06 gate-drain charge q gd 0.30 gate resistance r g f = 1 mhz 0.2 1 1.7 ? tu r n - o n d e l ay t i m e t d(on) v dd = 10 v, r l = 20 ? i d ? 0.5 a, v gen = 4.5 v, r g = 6 ? 10 20 ns rise time t r 16 30 turn-off delaytime t d(off) 10 20 fall time t f 10 20 source-drain reverse recovery time t rr i f = 0.23 a, di/dt = 100 a/s 20 40 output characteristics 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v gs = 5 v thru 2.5 v 2 v v ds - drain-to-source voltage (v) - drain current (a) i d 1.5 v 1 v transfer characteristics 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 t c = 125 c - 55 c 25 c v gs - gate-to-source voltage (v) - drain current (a) i d
document number: 71080 s11-2043-rev. j, 17-oct-11 www.vishay.com 3 vishay siliconix SI1902DL typical characteristics (25 c, unless otherwise noted) on-resistance vs. drain current gate charge surge-drain diode forward voltage - on-resistance ( ? ) r ds(on) 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 i d - drain current (a) v gs = 2.5 v v gs = 4.5 v 0 1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 v ds = 10 v i d = 0.66 a - gate-to-source voltage (v) q g - total gate charge (nc) v gs 0 0.2 0.4 0.6 0.8 1.0 1.2 t j = 150 c t j = 25 c 1 0.1 v sd - source-to-drain voltage (v) - source current (a) i s capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 20 40 60 80 100 0 4 8 121620 v ds - drain-to-source voltage (v) c rss c oss c iss c - capacitance (pf) 0.6 0.8 1.0 1.2 1.4 1 . 6 - 50 - 25 02 5 5 0 7 5 100 125 150 v gs = 4.5 v i d = 0.66 a t j - junction temperature (c) (normalized) - on-resistance r ds(on) 0.0 0.2 0.4 0.6 0.8 1.0 012345 i d = 0.66 a - on-resistance ( ? ) r ds(on) v gs - gate-to-source voltage (v)
www.vishay.com 4 document number: 71080 s11-2043-rev. j, 17-oct-11 vishay siliconix SI1902DL this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71080 . threshold voltage - 0.4 - 0.3 - 0.2 - 0.1 0 0.1 0.2 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v ariance (v) v gs(th) t j - temperature (c) single pulse power, junction-to-ambient 0 3 5 1 2 power (w) time (s) 4 1 100 600 10 10 -1 10 -2 10 -3 normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized ef fective t ransient thermal impedance 1. duty cycle, d = 2. per unit base = r th ja = 400 c/w 3. t jm - t a = p dm z th ja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 110 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized ef fective t ransient thermal impedance
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1
dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
an814 vishay siliconix document number: 71237 12-dec-03 www.vishay.com 1 dual-channel little foot sc-70 6-pin mosfet recommended pad pattern and thermal performance introduction this technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel little foot power mosfets in the sc-70 package. these new v ishay siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 250 ma) need to be switched, either directly or by using a level shift configuration. v ishay provides these devices with a range of on-resistance specifications in 6-pin versions. the new 6-pin sc-70 package enables improved on-resistance values and enhanced thermal performance. pin-out figure 1 shows the pin-out description and pin 1 identification for the dual-channel sc-70 device in the 6-pin configuration. figure 1. sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view s 1 g 1 d 2 d 1 g 2 s 2 for package dimensions see outline drawing sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) basic pad patterns see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the 6-pin sc-70. this basic pad pattern is sufficient for the low-power applications for which this package is intended. for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 20% when using a 1-inch square with full copper on both sides of the printed circuit board (pcb). evaluation boards for the dual sc70-6 the 6-pin sc-70 evaluation board (evb) measures 0.6 inches by 0.5 inches. the copper pad traces are the same as described in the previous section, basic pad patterns . the board allows interrogation from the outer pins to 6-pin dip connections permitting test sockets to be used in evaluation testing. the thermal performance of the dual sc-70 has been measured on the evb with the results shown below. the minimum recommended footprint on the evaluation board was compared with the industry standard 1-inch square fr4 pcb with copper on both sides of the board. thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the dual sc-70 6-pin package measured as junction-to-foot thermal resistance is 300 c/w typical, 350 c/w maximum. the ?foot? is the drain lead of the device as it connects with the body. note that these numbers are somewhat higher than other little foot devices due to the limited thermal performance of the alloy 42 lead-frame compared with a standard copper lead-frame. junction-to-ambient thermal resistance (dependent on pcb size) the typical r ja for the dual 6-pin sc-70 is 400 c/w steady state. maximum ratings are 460 c/w for the dual. all figures based on the 1-inch square fr4 test board. the following example shows how the thermal resistance impacts power dissipation for the dual 6-pin sc-70 package at two different ambient temperatures.
an814 vishay siliconix www.vishay.com 2 document number: 71237 12-dec-03 sc-70 (6-pin) room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 400 o c w p d 312 mw p d t j(max) t a r ja p d 150 o c 60 o c 400 o c w p d 225 mw note: although they are intended for low-power applications, devices in the 6-pin sc-70 will handle power dissipation in excess of 0.2 w. testing to aid comparison further, figure 2 illustrates the dual-channel sc-70 thermal performance on two different board sizes and two different pad patterns. the results display the thermal performance out to steady state. the measured steady state values of r ja for the dual 6-pin sc-70 are as follows: little foot sc-70 (6-pin) 1) minimum recommended pad pattern (see figure 2) on the evb of 0.5 inches x 0.6 inches. 518 c/w 2) industry standard 1? square pcb with maximum copper both sides. 413 c/w time (secs) figure 2. comparison of dual sc70-6 on evb and 1? square fr4 pcb. thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 1? square fr4 pcb dual evb 400 the results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to 20%. this fact confirms that the power dissipation is restricted with the package size and the alloy 42 leadframe. associated document single-channel little foot sc-70 6-pin mosfet copper leadframe version, recommended pad pattern and thermal performance, an815, (http://www.vishay.com/doc?71334) .
application note 826 vishay siliconix www.vishay.com document number: 72602 18 revision: 21-jan-08 application note recommended minimum pads for sc-70: 6-lead 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.067 (1.702) 0.026 (0.648) 0.045 (1.143) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.
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